News Highlights:
- A new generation of processor cores offering a high level of
performance and efficiency for applications across the home
entertainment, networking, mobile and embedded segments
- High-performance proAptiv™ core achieves the highest
CoreMark/MHz score reported for any licensable IP core, together
with leading silicon efficiency
- Multi-threaded interAptiv™ core delivers leading performance
efficiency, achieving higher CoreMark/MHz than competing cores in
similar die area
- Highly-efficient microAptiv™ core achieves highest CoreMark/MHz
score among microcontroller-class cores; adds DSP acceleration and
security
- Several lead licensees already signed for Aptiv™ cores
MIPS Technologies, Inc. (Nasdaq:MIPS), a leading provider
of industry-standard processor architectures and cores for home
entertainment, networking, mobile and embedded applications, today
introduced a new generation of microprocessor cores. The Aptiv
Generation cores, including the proAptiv, interAptiv and microAptiv
families, offer three distinct performance levels for applications
across MIPS' target segments.
All based on the MIPS32® Release 3 architecture, the products
are targeted to build on MIPS' leadership position in home
entertainment, strengthen its position in networking, extend the
company's offering in the high-volume embedded systems segment, and
provide a highly-competitive alternative for mobile system
development. For mobile devices, the Aptiv Generation offers
top-end multicore performance for applications processing in
products including tablets and smartphones, efficient
multi-threading technology for applications such as baseband
processing, and entry-level performance for embedded control and
applications such as touchscreen controllers, SIM/security and
GPS.
proAptiv Family Key Features
- Leading high-end CPU performance efficiency delivering over 4.4
CoreMark/MHz and 3.5 DMIPS/MHz1 in considerably smaller area
compared to competing IP cores2
- Ideal for applications processing in connected consumer
electronics such as high-end mobile devices and "smart" home
entertainment products, and control plane processing in networking
applications
- Efficient top-end performance minimizes the need for exotic
power management schemes such as "big.LITTLE" in many mobile
applications
- 60-75% higher performance on CoreMark and DMIPS scores compared
to MIPS32 74K™/1074K™ superscalar single/multicore products
- Highly-scalable solution leveraging one or more threads per
core, and up to six cores connected in a multi-core Coherent
Processing System (CPS)
- Major architectural features and enhancements:
- High-performance multi-issue, deeply out-of-order (OoO)
architecture with state-of-the-art branch prediction
- New higher-performance floating point unit (FPU) with higher
synthesizable frequency for 1:1 clock with core and native
double-precision execution
- Single-core and multi-core (up to six core) configurations
- Performance-enhanced, tightly-integrated second generation
Coherence Manager and L2 cache controller with lower total
latency
- MIPS Digital Signal Processing (DSP) Application Specific
Extension (ASE) v2
- Enhanced Virtual Address (EVA) for efficient 32-bit address map
utilization to reach 3GB+ user space
interAptiv Family Key Features
- The interAptiv core leverages a balanced nine-stage pipeline
with multi-threading to deliver leading performance efficiency,
achieving greater than 50% more CoreMark/MHz than competing cores
in similar die area1,2
- Ideal for highly-parallel applications requiring cost and power
optimization, such as smart gateways, baseband processing in LTE
user equipment and small cells, SSD controllers and automotive
equipment
- Highly-scalable solution leveraging one or more threads per
core, and up to four cores connected in a multi-core Coherent
Processing System (CPS)
- Features and enhancements
- Multi-threaded pipeline implements dual virtual processors,
appearing as two complete CPUs to an SMP Linux operating
system
- Hardware Quality of Service (QoS), thread management support
and inter-thread communication enable optimal control for real-time
applications
- Performance-enhanced, tightly-integrated second generation
Coherence Manager and L2 cache controller with lower total
latency
- Support for up to two I/O coherency units
- Core and CPS-level power management features
- Error Checking and Correction (ECC) support in L1 data cache,
L2 cache and data SPRAM
- Enhanced Virtual Address (EVA) for efficient 32-bit address map
utilization to reach 3GB+ user space
- Optional floating point unit
microAptiv Family Key Features
- Low-power, compact, real-time embedded processor core with
integrated standard I/O interfaces, building on popular MIPS32
M14K™ core family with microMIPS™ code compression instruction set
architecture
- Integrates DSP and SIMD functionality to address signal
processing requirements for a wide range of embedded segments
including industrial control, smart meters, automotive and
wired/wireless communications
- Leverages highly-efficient 5-stage pipeline to achieve 3.09
CoreMark/MHz and 1.57 DMIPS/MHz1 in microMIPS mode, with 40% and
25% higher performance, respectively, compared to competition2
- MCU and MPU (with integrated cache controller/MMU) product
versions available for microcontroller and embedded applications
- Compared to previous generation MIPS cores and competitive
cores, offers greater range of design features for both control and
DSP operations
- New memory protection unit for enhanced program code and data
security, microMIPS-only execution mode, secure debug and 2-wire
cJTAG support
About the CoreMark™ Benchmark
The CoreMark benchmark, developed by EEMBC, is a simple yet
sophisticated benchmark that is designed specifically to test the
functionality of a processor core. Running CoreMark produces a
single-number score allowing users to make quick comparisons
between processors. For more information, visit
http://www.coremark.org.
Product Specifications and Details
For detailed product information including benchmarks,
specifications, datasheets and more, visit www.mips.com/aptiv.
Availability
All Aptiv core families can be licensed now. The proAptiv family
will be generally available in mid-2012 supporting a range of
functional and performance points with single and multi-core
versions. The new proAptiv FPU is also available. The interAptiv
family will be available in mid-2012 in dual- and quad-core
configurations, with optional FPU. Single core versions will be
available in the fourth quarter. The microAptiv family is available
now, with cache/MMU or non-cached core options. For more
information on product availability, contact info@mips.com, or
visit www.mips.com/aptiv.
Supporting Quotes
"With the launch of our new Aptiv Generation of products, MIPS
is entering a new era of innovation and increasing our competitive
position. The Aptiv Generation is the result of strategic
investments we have made, and are continuing to make for the
future. We are pushing performance efficiency to new levels. Our
previous generation of cores was already more performance-efficient
than the competition. The new Aptiv Generation is even better. With
these cores and the ever-expanding ecosystem around the MIPS
architecture, we are providing solutions that will enable our
customers to differentiate and win in an increasingly competitive
market."
—Gideon Intrater, Vice President of Marketing,
MIPS Technologies
"The preliminary CoreMark benchmark scores that MIPS is
reporting for their new proAptiv core indicate that a
deeply-pipelined CPU isn't necessarily penalized by the control
operations inherent within CoreMark. EEMBC created CoreMark as a
more realistic measurement of CPU performance than ineffective
alternatives such as DMIPS. We are enthusiastic about MIPS' support
for CoreMark as the new standard for measuring baseline CPU
performance, and congratulate MIPS on reaching new performance
heights."
—Markus Levy, President, EEMBC
"Microprocessor technology continues to evolve to address
rapidly-increasing demands for processing power across applications
that range from low-power mobile devices to high-performance
networking products. MIPS' new Aptiv Generation introduces a lineup
of CPU cores with the performance and power efficiency to address
this broad range of markets. The specs of the new proAptiv core in
particular show it to be a major step forward in performance,
dramatically improving CoreMark/MHz while maintaining the power and
area efficiency that we have come to expect from the MIPS
architecture."
—J. Scott Gardner, Senior Analyst, The Linley
Group / Microprocessor Report
"With Arteris' advanced network-on-chip interconnect technology,
MIPS' customers in automotive and consumer electronics have
improved performance, timing closure, power consumption and die
size of their SoCs. We look forward to supporting mutual customers
developing advanced next-generation SoCs based on MIPS' new Aptiv
Generation of cores."
—Kurt Shuler, Vice President of Marketing,
Arteris
"Carbon's solutions are targeted to accelerate our customers'
time to market by providing the most productive and cost effective
unified virtual platform solutions in the industry. We have long
supported MIPS cores with our 100% cycle accurate models, and we
are pleased to announce our planned support for the new Aptiv
cores. With Carbon's system level modeling and validation tools for
MIPS processor cores, customers can perform architectural analysis
and validation, and achieve pre-silicon firmware optimization and
hardware-software system validation.
—Bill Neifert, CTO, Carbon Design Systems
"Express Logic and MIPS Technologies have worked closely
together for many years, enabling embedded developers to get to
market quickly with the powerful combination of our ThreadX® RTOS
on MIPS cores. ThreadX is an ideal solution for deeply embedded
systems where small code size and real-time performance are
critical. MIPS cores that leverage the microMIPS ISA, such as the
new microAptiv core, offer a compelling solution for these systems,
and we will continue to support these cores for our common
customers. In addition, because ThreadX SMP supports the MIPS'
multi-threading and multiprocessing technologies, designers can
increase their productivity when developing real-time applications
that utilize these platforms."
—William E. Lamie, CEO, Express Logic, Inc.
"We have partnered with MIPS since 2001, providing designers of
MIPS-Based systems with support from a wide range of development
tools and RTOS software. We look forward to continuing our
relationship with MIPS by offering support of its new interAptiv
family in our compiler, MULTI Integrated Development Environment
and debug probes."
—Mike Haden, General Manager, Advanced Products,
Green Hills Software
"Imagination's market leading technologies, including PowerVR
graphics and video and Ensigma multistandard communications, have
all been combined with processor IP from MIPS Technologies to
enable our numerous partners to bring to market successful SoCs for
next-generation devices. With Imagination's IP, MIPS' licensees can
create products that deliver world-class multimedia and
communications performance coupled with low power and low cost — a
key requirement for tomorrow's mobile and smart connected
applications. We look forward to working with MIPS and our mutual
customers on next-generation solutions based on the new Aptiv
Generation of products."
—Tony King-Smith, VP marketing, Imagination
Technologies
"As part of the continued cooperation between Imperas and MIPS,
we are excited to already have support for the new Aptiv cores in
our Open Virtual Platforms™ (OVP™) and
Multiprocessor/Multicore/Multithread Software Development Kit
(M*SDK™). The instruction accurate OVP Fast Processor Models of the
MIPS' cores enable users to integrate these models into both OVP
and SystemC/TLM-2.0 virtual platform environments. The models for
the MIPS cores support both the MIPS32 and microMIPS instruction
sets as appropriate, as well as extensions for capabilities such as
floating point, DSP and multi-threading."
—Simon Davidmann, CEO, Imperas
"We are pleased to see MIPS grow its portfolio of
multi-threading cores, and congratulate the company on its new
Aptiv Generation of processor cores. MIPS' multi-threaded
technology has delivered strong results for Lantiq's Gateway
Solutions, enabling us to maximize performance while minimizing
power usage and system costs. Our Gateway Solutions address system
configurations ranging from cost-optimized fast Ethernet to
feature-rich, high-performance Gigabit Ethernet systems, and are
designed to enhance and extend telecom carriers' xDSL services in
worldwide markets. Lantiq's Gateway Solutions enable carriers to
meet the growing demand for triple-play services and in-home
Gigabit throughput with significant cost, size and power savings at
no system performance compromise."
—Rainer Spielberg, Vice President of Marketing,
Lantiq
"With our TRACE32® In-Circuit Debugger, Lauterbach supports all
of MIPS' classic processor cores, and we are already offering
support for the complete range of debug features in its new
microAptiv cores. We look forward to supporting the rest of the
Aptiv Generation cores. Through our relationship with MIPS
Technologies, developers working with MIPS cores will have access
to a full range of debug functionality."
—Norbert Weiss, International Sales &
Marketing Manager, Lauterbach GMBH
"Mentor Graphics is pleased to enable the development of Linux
and RTOS-based embedded systems with MIPS' new Aptiv Generation of
cores. The Sourcery CodeBench validated GNU toolchain enables
developers to easily build and debug embedded applications based on
both Mentor Embedded Linux and the Mentor Embedded Nucleus RTOS.
Developers can take advantage of MIPS' multi-threading technology
through the efficient Nucleus RTOS with VSMP capability. We are
pleased to continue our relationship with MIPS by extending our
broad support of MIPS architecture and tools."
—Glenn Perry, General Manager, Mentor Graphics
Embedded Software Division
"Microchip Technology's embedded design customers continue to
benefit from our successful relationship with MIPS Technologies,
via our best-in-class portfolio of 32-bit PIC32 microcontrollers
built around the industry-leading MIPS architecture. For
microcontrollers, MIPS provides superior performance and more
advanced features than the competition. We are pleased to see the
launch of MIPS' newest microAptiv cores, which fulfill
next-generation application demands for 32-bit DSP performance and
increased functionality."
—Sumit Mitra, MCU32 Division Vice President,
Microchip Technology Inc.
"Mobileye has had great success using MIPS' multi-threaded cores
in our EyeQ2™ processor for vision based driver assistance systems,
helping us achieve a 6x performance gain over our previous
solution. Automotive safety applications require extreme
reliability and real-time performance. These needs have been more
than well-met by MIPS' multi-threading architecture, which greatly
aids in image processing and offers ECC for enhanced reliability.
We are excited that MIPS continues to build on its unique and
powerful multi-threading technology, and we look forward to its new
interAptiv core."
—Elchanan Rushinek, Senior VP, Engineering,
Mobileye
"MIPS' newest multi-threaded interAptiv processor cores provide
the high performance, low power, and scalability needed for many
storage and networking applications. Multi-threading enables PMC to
develop products that outperform competing solutions, and we will
continue to deliver the power and performance that our customers
require for their next-generation systems."
—Salman Ghufran, VP, Product Development, PMC®
"Sonics and MIPS have a long-standing relationship and have
partnered on numerous, successful SoCs developed by mutual
customers. As the world's number one supplier of on-chip network IP
for advanced SoCs, Sonics looks forward to expanding this
relationship in support of MIPS' new Aptiv generation of cores.
With Sonics' innovative on-chip network technology, MIPS processor
cores can connect seamlessly with other IP blocks throughout the
SoC. Today, this is already demonstrated in MIPS' FPGA
implementations of its new Aptiv cores, where Sonics' provides the
advanced on-chip network."
—Jack Browne, Senior Vice President of Sales and
Marketing, Sonics, Inc.
"Synopsys collaborated with MIPS to optimize the performance of
MIPS' next generation processor cores. By using the Galaxy™
Implementation Platform together with DesignWare® Embedded Memories
and Logic Libraries tuned for high-performance processors,
designers can now maximize performance and minimize energy
consumption of their MIPS-Based SoCs. We continue to work with MIPS
to lower designers' integration risk and speed delivery of their
SoC products to market."
—Rich Goldman, Vice President, Corporate Marketing
& Strategic Alliances, Synopsys
"We are pleased to support the MIPS architecture with our
embedded virtualization technology. Our PikeOS™ RTOS is a
hypervisor virtualization platform that allows several applications
and operating systems such as Android™ and Linux to run securely in
parallel on a single hardware platform. With PikeOS, MIPS'
licensees have flexibility in deploying CPU resources for different
tasks, potentially eliminating the need for a dedicated security
CPU in their system. Licensees of MIPS' Aptiv Generation of cores
will soon be able to reap the benefits of this compelling
technology."
—Jacques Brygier, Vice President of
Marketing, SYSGO AG
About MIPS Technologies, Inc.
MIPS Technologies, Inc. (Nasdaq:MIPS) is a leading provider of
industry-standard processor architectures and cores for home
entertainment, networking, mobile and embedded applications. The
MIPS architecture powers some of the world's most popular products.
Our technology is broadly used in products such as digital
televisions, set-top boxes, Blu-ray players, broadband customer
premises equipment (CPE), WiFi access points and routers,
networking infrastructure and portable/mobile communications and
entertainment products. Founded in 1998, MIPS Technologies is
headquartered in Sunnyvale, California, with offices worldwide. For
more information, contact (408) 530-5000 or visit www.mips.com.
Follow MIPS on Facebook, LinkedIn, YouTube, RSS, Twitter
and MIPS Blog.
The MIPS Technologies, Inc. logo is available at
http://www.globenewswire.com/newsroom/prs/?pkgid=11351
MIPS, MIPS32, 74K, 1074K, M14K, Aptiv, microAptiv, interAptiv,
proAptiv, microMIPS and MIPS-Based are trademarks or registered
trademarks in the United States and other countries of MIPS
Technologies, Inc. CoreMark is a trademark of EEMBC and EEMBC is a
registered trademark of the Embedded Microprocessor Benchmark
Consortium, a non-profit organization that develops certifiable
benchmarks for embedded processors and systems. Android is a
trademark of Google Inc. Use of this trademark is subject to Google
Permissions. All other trademarks referred to herein are the
property of their respective owners.
Footnotes:
1 The Dhrystone 2.1 and CoreMark 1.0 numbers were achieved using
Mentor Sourcery CodeBench v2011.03-94, gcc 4.5.2
2 Based on publicly available information from ARM, CoreMark
scores from EEMBC CoreMark website, and material available on the
Internet
CONTACT: Media Contact:
Jen Bernier-Santarini
MIPS Technologies
+1 408-530-5178
jenb@mips.com
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