BOSTON, April 18,
2024 /PRNewswire/ -- Semiconductor packaging has
evolved from traditional 1D PCB levels to cutting-edge 3D hybrid
bonding at the wafer level, achieving interconnecting pitches as
small as single micrometers and over 1000 GB/s bandwidth. Key
parameters, including Power, Performance, Area, and Cost, are
crucial considerations. Power efficiency is enhanced through
innovative packaging techniques, while Performance benefits from
shorter interconnection pitches. Area requirements vary for
high-performance chips and 3D integration's smaller z-form factor.
Cost reduction strategies involve exploring alternative materials
and improving manufacturing efficiency. In the realm of 3D
integration, microbump technology continues to advance for
achieving smaller pitches, with groundbreaking Cu-Cu connection
methods like hybrid bonding leading the way, achieving <1
micron-level pitches. This article introduces Cu-Cu hybrid
technology, including its development, the high-level methodology
to achieve it, and key applications. This article shares some of
the research from the IDTechEx report, "Advanced Semiconductor
Packaging 2024-2034: Forecasts, Technologies, Applications."
Introduction to microbump and hybrid bonding
technology
Microbump technology, a well-established technology in
semiconductor packaging, relies on the Thermal Compression Bonding
(TCB) process and has a widespread application across various
products. Its evolutionary path primarily revolves around
continually scaling bumping pitch. However, a significant hurdle
arises as the shrinking solder ball sizes lead to heightened
formation of Intermetallic Compounds (IMCs), consequently
compromising conductivity and mechanical properties. Moreover, the
proximity of contact gaps may induce solder ball bridging during
reflow, posing a risk of chip failure. Since solder and IMCs
exhibit higher resistivity than copper, their utilization in
high-performance component packaging encounters limitations.
On the other hand, hybrid bonding presents a paradigm shift by
establishing interconnections through a combination of dielectric
material (for example, SiO2 or SiCN) and embedded metal (Cu).
Notably, Cu-Cu hybrid bonding has achieved pitches below 10
micrometers, typically around single-digit µm values. This
advancement brings forth several benefits, including expanded I/O,
heightened bandwidth, improved 3D vertical stacking, enhanced power
efficiency, and reduced parasitics and thermal resistance
attributed to the absence of underfill. However, challenges persist
in the form of manufacturing complexities and elevated costs
associated with this advanced technique.
Three ways of Cu-Cu hybrid bonding
There are three primary methods for achieving hybrid bonding:
die-to-die (D2D), die-to-wafer (D2W), and wafer-to-wafer (W2W).
Each approach offers distinct advantages and disadvantages,
influencing its suitability for various applications.
Die-to-Die bonding offers the highest assembly yield since both
dies can undergo individual testing before bonding. This method
also provides the highest design flexibility. However, it suffers
from very low throughput and presents significant challenges during
the process, particularly regarding edge effects, contamination,
and particles introduced during singulation. Additionally,
die-to-die bonding requires pick & place equipment with
exceptionally high accuracy. Due to these manufacturing challenges
and low throughput, this method currently has limited commercial
use in hybrid bonding applications.
Wafer-to-wafer bonding stands out for its highest throughput,
which is crucial in the semiconductor industry. Its process steps
are simpler compared to die-to-die bonding, as it eliminates the
need for cutting dies and pick and place procedures. However,
wafer-to-wafer bonding may result in lower yield and reduced design
flexibility, as the top and bottom dies must be the same size.
Despite these drawbacks, wafer-to-wafer bonding remains the most
commonly employed approach for Cu-Cu hybrid bonding in current
commercial applications.
Die-to-wafer bonding occupies a middle ground between die-to-die
and wafer-to-wafer methods. This approach provides higher design
flexibility and yield compared to wafer-to-wafer bonding. However,
it faces challenges related to lower throughput and more complex
processing requirements. Despite these challenges, die-to-wafer
bonding has gained momentum due to its ability to strike a balance
between design flexibility and manufacturing efficiency.
Overall, the choice of hybrid bonding method depends on factors
such as assembly yield requirements, design flexibility, throughput
considerations, and processing challenges. Each approach offers
distinct trade-offs, shaping its applicability in semiconductor
packaging and integration.
How hybrid bonding is implemented in HPC chips
The most prominent adoption of hybrid bonding is AMD employing
TSMC's 3D SOIC (hybrid bonding) technology for stacking L3 cache
die onto a computing chip in two product lines: the consumer AMD
Ryzen 7000X3D CPU for desktops (incl. AMD Ryzen™ 9 7950X3D and AMD
Ryzen 7 5800X3D) and the EPYC processor for high-performance
computing (HPC). AMD emphasizes hybrid bonding's role in surpassing
their power efficiency goals with chiplet and 3D-enabled
architecture. They highlight its superiority over micro bump 3D
technology, citing 15 times higher interconnect density and 3 times
greater energy efficiency. Other examples include Graphcore's Bow
Intelligence Processing Unit (BOW) is the world's first 3D
Wafer-on-Wafer (WoW) processor, utilizing TSMC 7 nm technology and
TSMC 3D SoIC technology for a 3D die, featuring 1,472 IPU-Core
tiles with 900MB of in-processor memory, offering up to 40% faster
AI performance and 16% better performance-per-Watt compared to its
2D predecessor. Another key example is the utilization of hybrid
bonding in high-bandwidth memory (HBM). Major players in the HBM
market, such as SK Hynix, Samsung, and Micron, are increasingly
exploring hybrid bonding for their applications. While microbump
stacking has been the traditional method in HBM, the growing demand
for enhanced bandwidth expansion and power efficiency is driving
the active investigation of hybrid bonding. The commercialization
of hybrid bonding-based HBMs is expected in the next generation or
thereafter, offering a substantial competitive advantage over
microbump-based alternatives. This provides these competitors with
a strong edge against the current market leader.
Summary
Hybrid bonding is poised to revolutionize the landscape of
future HPC and AI products, offering a host of advantages that will
shape the industry's path forward. As technology advances and
demands for increased computing power and efficiency continue to
surge, hybrid bonding emerges as a key enabler for meeting these
evolving needs.
The IDTechEx report, "Advanced Semiconductor Packaging
2024-2034: Forecasts, Technologies, Applications", delves into the
dynamic landscape of 2.5D and 3D semiconductor packaging, analyzing
technology trends, industry barriers, and market forecasts across
AI, HPC, 5G/6G, autonomous vehicles, and consumer electronics
sectors. With unbiased analysis and detailed market evaluations,
this report provides a comprehensive understanding of the
industry's future, making it essential reading for stakeholders
navigating the evolving semiconductor landscape.
To find out more about the "Advanced Semiconductor Packaging
2024-2034: Forecasts, Technologies, Applications" report, including
downloadable sample pages, please visit www.IDTechEx.com/ASP.
For a deeper understanding of materials and processing in Cu-Cu
hybrid bonding, refer to IDTechEx's related report, "Materials and
Processing for Advanced Semiconductor Packaging 2024-2034". This
report offers valuable insights into manufacturing processes,
material selection, and successful case studies, aiding
stakeholders in achieving optimal outcomes.
To find out more about the "Materials and Processing for
Advanced Semiconductor Packaging 2024-2034" report, including
downloadable sample pages, please visit
www.IDTechEx.com/MatsforASP.
For the full portfolio of semiconductor market research from
IDTechEx, please visit
www.IDTechEx.com/Research/Semiconductors.
About IDTechEx:
IDTechEx provides trusted independent research on emerging
technologies and their markets. Since 1999, we have been
helping our clients to understand new technologies, their supply
chains, market requirements, opportunities and forecasts. For more
information, contact research@IDTechEx.com or
visit www.IDTechEx.com.
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